1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of fabrication of semiconductor devices.
2. Background Art
Due to its numerous advantages, such as high density, low power consumption, and relative noise immunity, for example, complementary metal-oxide-semiconductor (CMOS) technology is widely used in control logic circuits, and in analog circuits implemented as part of the integrated circuits (ICs) used in modern electronic systems. As advancements in process technologies have resulted in CMOS devices being scaled down, and their operating voltages correspondingly reduced, device features have evolved to include, for example, high dielectric constant (high-k) metal gate designs.
Mismatch is particularly critical to analog device performance. A conventional fabrication strategy responsive to the problem of mismatch employs the use of relatively long channel lengths, e.g., channel lengths of 0.5 μm or greater, to lower its incidence in analog metal-oxide-semiconductor field-effect transistors (MOSFETs). However, the use of long channels as a solution to analog device mismatch is incompatible with the progressive advancement of process technologies towards ever reduced device dimensions.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by delivering a solution compatible with existing high-k metal gate CMOS fabrication process flows, which enables concurrent fabrication of low mismatch analog devices.